Understanding your new ChronoVu USB Logic Analyzer

Before you are ready to start probing digital busses using your new ChronoVu logic analyzer , it is important to understand the operation, capability and limitations of the equipment, as well as a few general concepts regarding the acquisition and analysis of electrical signals. As is the case with most tools, many hours of frustration can be replaced by a few minutes of instruction.

What does it do?

The ChronoVu USB logic analyzer is a tool designed to monitor and display the electrical communications between components in a digital circuit. It does this by monitoring the voltage levels on multiple inputs as a function of time, and by providing the means to control the timing of the data acquisition and the display of the resulting information, such that an engineer or technician can effectively eavesdrop on these digital conversations using Windows, Linux, or Mac platforms.

Test Lead Connection

The ChronoVu analyzer measures the voltage at each input or “channel” relative to the voltage at the ground channel connection. It is, therefore, necessary that the ground channel(s) marked “G” be connected to a grounded node on the device under test if meaningful measurements are to be made on any of the 8-16 input channels. Once the ground channel(s) has been connected, each of the 8-16 input channels can be connected to a different signal node in order to simultaneously monitor the digital state of up to 8 or 16 signals as a function of time.

Digital Signal Levels

Your ChronoVu logic analyzer inputs are designed to be compatible with the majority of modern digital IC’s including standard CMOS, TTL, LVTTL, and LVCMOS bus specifications. Any measured voltage between 0V and 0.8V will be considered an electrical zero, whereas any voltage between 2.0V and 5.5V will be considered an electrical one.

Signal Loading

Although the ChronoVu logic analyzer inputs are designed to “invisibly” monitor voltage levels, a nominal input current (about one-hundred microamps) is required to switch the input from one logic state to another. The purpose of this “hysteresis current” is to insure that unconnected ChronoVu inputs are stable, and to produce cleaner results when very low speed signals are probed. In addition to this “hysteresis current” load, the ChronoVu input presents a capacitive load of approximately 5pf on the monitored bus.

Acquisition Trigger

Eavesdropping on an electrical bus is not unlike eavesdropping on any other conversation, in that it is frequently necessary to ignore the conversation until a key word is heard. The acquisition trigger word, which can be specified on the Acquisition Setup menu, is the key word that will tell the ChronoVu logic analyzer to start recording data for subsequent analysis. When the ChronoVu analyzer is enabled, data will be monitored but ignored until the specified trigger word is observed. Once triggered, the analyzer will acquire and store a total of 8,388,608 readings per channel for LA8 or 4,194,304 readings per channel for LA16.  Unless the trigger word is observed immediately when the analyzer is enabled, the recorded sample window will include a small amount of pre-trigger data. When the data is displayed, “time zero” will be, by definition, the time at which the trigger word was observed, hence the time axis will always indicate the amount of time since the trigger event. Accordingly, the pre-trigger data will be displayed at negative values on the time axis.

Sample Rate

The ChronoVu logic analzyer accurately assesses the logic state of the inputs as a function of time by repeatedly measuring the voltage level on its inputs at a carefully controlled rate. The rate at which voltage readings are taken is software selectable from the Acquisition Setup menu. The rate can be as fast as one reading every 10 nanoseconds for LA8 or 5 nanoseconds for LA16 and as slow as one reading every 2.55 microseconds. Obviously, the resolution of the measured signal timing, as well as the size of the minimum reliably detectable pulse, is determined by the sample rate, so a sample rate must be chosen which is fast compared to the frequency of the probed signal. Once triggered, the logic analyzer will acquire and store a sample window consisting of 8,388,608 readings per input signal for LA8 or 4,194,304 readings per input signal for LA16, thus the total acquisition time will be dependant upon the sample rate selected. If the sample rate is too slow, time accuracy will suffer and valuable information might be missed, however if the sample rate is too fast, the duration of the sample window may be too short to include all of the desired information. A sample rate five to ten times faster than the data frequency on the probed bus is generally ideal, however a faster or slower sample rate can be used when better time resolution or a longer signal window is required.