Preparing to analyze a digital bus
Once the data has been acquired and saved, it can be recalled and analyzed at any time. Sometimes just a glance at the signals is all the analysis required, but frequently it is useful to consider several channels as different bits in a parallel bus, or treat consecutive pulses as bits in a serial communication. The ChronoVu bus analysis tools are designed to simplify these bus analyses, by interpreting and displaying a selected group of signals as a human readable bus, so that your time can be spent debugging your circuitry rather than decoding the bus communications. This tutorial is intended to be a brief introduction to the bus analysis tools. For a much more detailed discussion, see the Bus Analysis Setup help page.
Select appropriate data bus settings
Parallel or Serial
Serial busses communicate using a single data channel (albeit sometimes a two-wire data channel) over which words are transmitted as a group of pulses. Parallel busses communicate using multiple data channels to simultaneously transmit the multiple bits composing a data word. Begin by selecting whether your bus is a parallel or serial communication bus. (See Bus Analysis Setup for assistance).
Asynchronous, Synchronous, or Timed
Select the manner in which your bus communications are timed. Asynchronous busses are data-timed busses where successive data pulses are differentiated by the recognition that the data state has changed. For synchronous busses, the data pulse timing is provided by one or more specific clock signals which are monitored on one or more of the ChronoVu channels. Timed busses are intrinsically clocked busses, where successive data pulses are assumed to occur at predetermined intervals following a “strobe” or “enable” event. It is sometimes possible, and even useful, to interpret a given bus communication in more than one of these ways, however it is usually easiest to start by interpreting the bus in the fashion that the transmitting component intended. (See Bus Analysis Setup for assistance). Each category of bus has specific options and parameters, most of which will be discussed briefly below.
Data Channel Selection
Once the general bus type has been specified, one or more ChronoVu channels must be specified as the source of the bus data. On parallel busses, the data specification indicates which channels are to be mapped onto which bits in the parallel word. In serial busses, the data can be assigned to a single channel, or both a data channel and a data-bar channel can be simultaneously defined. (See Bus Analysis Setup for assistance).
Enable or Reset
Often, an electrical data bus will be accompanied by one or more enable signals to indicate when the bus is to be made active. If such signals exist, specify which ChronoVu channels are to be used to enable the bus, otherwise the always enabled option can be selected. Note that, for some types of busses, an enable or reset indicator is not optional, particularly where a reset is required to flag the beginning of a serial word or parallel data burst. For such cases, it is possible to specify a “reset on idle” condition using, for example, the data channels as reset (on idle) indicators. Bus enables or resets can, depending on bus type, be based upon multiple signal states, edges, or idle conditions. See the Bus Analysis Setup help file for further assistance.
For synchronous busses, the clock input channel(s) must be specifically specified. If more than one clock channel is specified, the bus will be clocked by any of the specified edges. Multiple pulse transfers, such as synchronous serial or synchronous parallel burst communications, will reset to the front of a new data transfer on the first clock following the bus reset or enable, and will start an additional transfer on the first clock following the end of the previous transfer. See the Bus Analysis Setup help file for further assistance.
For timed busses, the strobe input channel(s) must be specifically specified. Timed bus strobes can be data channels, enable channels, or specific timing signal channels. If more than one strobe channel is specified, the bus will be initiated by any of the specified edges. Multiple pulse transfers, such as timed serial or timed parallel burst communications, will always be initiated by the first occurrence of a strobe transition after the bus has been enabled or reset. The first bus clock will occur after the specified delay following the strobe transition. Additional bus clocks will then continue to occur at the specified clock period until the requested data transfer is completed. Additional strobe transitions within the delay-from-strobe period will restart the delay, however once the delay has been achieved, additional strobe transitions will have no effect on the clock timing until the data transfer has been completed. A new data transfer will be initiated on the next strobe transition following the end of a previous data transfer. See the Bus Analysis Setup help file for further assistance.
On asynchronous busses, the bus clock will occur once the data has become stable following one or more transitions on the data bus. The noise filter will specify the period of time that the data must remain stable before the bus will be clocked. This can be used to prevent skew between multiple data channels from producing unwanted bus clock events. On synchronous busses, the noise filter is applied to the clock inputs, preventing ringing or skew between multiple clock inputs from producing unwanted bus clock events.
Max Burst Duration / Max Word Duration
The max burst or word duration input is used to determine when to reset the bus when the reset-on-idle bus reset options are used. It is also used to determine how much data should be examined prior to the visible window to insure that the end of an ongoing burst or serial transfer is properly displayed in the signal display window.
Serial word or Parallel burst specification
For multiple pulse transfers, such as serial or parallel burst data transfers, the number of expected data pulses must be specified using the burst length or bus width parameter. For serial transfers, additional data channel pulses such as parity bits, stop bits, etc. can be specified using the postamble bits field. The burst order or bit order field is used to indicate the order of the data transfer – most significant word/bit first, or least significant word/bit first.
Bus Display Enable
Once the desired bus parameters have been specified, and the bus name and color have been adjusted (if desired), the bus visibility box must be checked to indicate that the bus analysis is to be enabled. If the bus visibility is enabled when the Bus Analysis Setup menu is closed, the bus will be evaluated and displayed. If the bus parameters are incomplete or inconsistent, an error will be issued, and the bus display will be disabled. Should this occur, the Bus Analysis Setup menu will need to be re-opened, and appropriate changes made, before the bus can be evaluated and displayed.
Buses are displayed as double lines with X’s where bus value transitions occur. Bus clocks are indicated by short vertical “tick marks” below the bus. These “tick marks” can be particularly useful when the bus clock is derived, such as is the case in timed busses, or when large values are used in the noise filter field. The last clock in any data transfer is indicated by a small vertical arrow rather than the tick mark. These arrows are particularly useful when multiple pulse busses are examined. Periods when the bus is disabled will be displayed as a bus with a single horizontal line through the center. Periods when the bus is indeterminate or invalid will be displayed as a bus with a double horizontal line through the center. Text indicating the value of a bus transfer will be displayed on the bus only if the zoom factor is sufficient to allow room for the text. Bus text can be displayed in hexadecimal format, ascii format, or decimal format. When the ascii format is selected, bus transfers of data that can not be converted into valid ascii characters will be displayed without text. As an example, a 4 bit parallel bus, executing a 4 word (4 nibble) timed burst, with the first bit delayed a full bit period from the strobe, ordered LSB first, and displayed in hexadecimal format, is illustrated below: